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74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger
Product specification IC24 Data Handbook 1998 Jun 17
Philips Semiconductors
Philips Semiconductors
Product Specification
Dual D-type flip-flop with set and reset; positive-edge trigger
FEATURES DESCRIPTION
74LVC74A
* Wide supply voltage range of 1.2 V to 3.6 V * In accordance with JEDEC standard no. 8-1A. * Inputs accept voltages up to 5.5 V * CMOS low power consumption * Direct interface with TTL levels * Output drive capability 50 W transmission lines @ 85C
The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC74A is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in all data inputs makes the circuit highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL PARAMETER Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Notes 1 and 2 CONDITIONS TYPICAL 3.6 3.5 3.5 250 5.0 30 UNIT
tPHL/tPLH fmax CI CPD
CL = 50 pF; VCC = 3.3 V
ns
MHz pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) + (VO2/RL) x duty factor LOW, where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC74A D 74LVC74A DB 74LVC74A PW NORTH AMERICA 74LVC74A D 74LVC74A DB 74LVC74APW DH DWG NUMBER SOT108-1 SOT337-1 SOT402-1
PIN CONFIGURATION
1RD 1D 1CP 1SD 1Q 1Q GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 2RD 2D 2CP 2SD 2Q 2Q
LOGIC SYMBOL (IEEE/IEC)
4 3 2 1 S C1 1D R 6
5
10 11 12
S C2 2D R
9
SV00491
13
8
SV00332
1998 Jun 17
2
853-2070 19589
Philips Semiconductors
Product Specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74A
PIN DESCRIPTION
PIN NUMBER 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1RD, 2RD 1D, 2D 1CP, 2CP 1SD, 2SD 1Q, 2Q 1Q, 2Q GND VCC NAME AND FUNCTION Asynchronous reset-direct input (active LOW) Data inputs Clock input (LOW-to-HIGH, edge triggered) Asynchronous set-direct input (active LOW) True flip-flop outputs Complement flip-flop outputs Ground (0 V) Positive supply voltage
FUNCTION TABLE
INPUTS SD L H L RD H L L INPUTS SD H H RD H H CP D L H CP X X X D X X X OUTPUTS Q H L H Q L H H
OUTPUTS Qn+1 L H Qn+1 H L
LOGIC SYMBOL
4 10 1SD 2SD SD 2 1D 1Q D Q 12 2D 2Q 3 1CP FF CP 11 2CP 1Q Q 2Q RD 1RD 2RD 1 13 5 9 5 9
NOTES: H = HIGH voltage level L = LOW voltage level X = don"t care = LOW-to-HIGH CP transition Qn+1 = state after the next LOW-to-HIGH CP transition
FUNCTIONAL DIAGRAM
4 2 3 1S D 1D 1CP D SD Q 1Q 5
CP FF1 Q RD 1Q 6
SV00492
1 1R D 10 12 11 2S D 2D 2CP D SD Q 2Q 9
CP FF2 Q RD 2Q 8
13 2RD
SV00494
1998 Jun 17
3
Philips Semiconductors
Product Specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74A
LOGIC DIAGRAM (ONE FLIP-FLOP)
Q C C
C C D C RD SD CP C C
C C Q C
SV00495
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 -40 0 0 MAX 3.6 3.6 5.5 VCC +85 20 10 UNIT V V V C ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t 0 Note 2 VO uVCC or VO t 0 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +5.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 500 500 UNIT V mA V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 17
4
Philips Semiconductors
Product Specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II ICC ICC Input leakage current Quiescent supply current Additional quiescent supply current per input pin VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0.1 "0 1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*1.0 0.40 0.20 0.55 "5 10 500 A A A V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500W; Tamb = -40_C to +85_C LIMITS SYMBOL PARAMETER Propagation delay nCP to nQ, nQ tPHL/ tPLH Propagation delay nSD to nQ, nQ Propagation delay nRD to nQ, nQ tW trem tsu th fmax Clock pulse width HIGH or LOW Set or reset pulse width LOW Removal time set or reset Set-up time nD to nCP Hold time nD to nCP Maximum clock pulse frequency WAVEFORM VCC = 3.3V 0.3V MIN Figures 1, 3 Figures 2, 3 Figures 2, 3 Figure 1 Figure 2 Figure 2 Figure 1 Figure 1 Figure 1 1.5 1.5 1.5 3.3 3.3 1 2.0 1 150 TYP1 3.6 3.5 3.5 1.3 1.7 -3 0.8 -0.7 250 MAX 5.2 5.4 5.4 - - - - - - VCC = 2.7V MIN - - - - - - - - - MAX 6.0 6.4 6.4 - - - - - - ns ns ns ns ns ns ns MHz UNIT
NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25C.
1998 Jun 17
5
Philips Semiconductors
Product Specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74A
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V VM = 0.5 S VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load.
VI nD INPUT GND t su VI nCP INPUT GND VM tW t PHL VM t PLH VM th 1/f max t su th
TEST CIRCUIT
VCC S1 2 * VCC Open GND
500 VI PULSE GENERATOR RT D.U.T. VO
50pF
CL
500
SWITCH POSITION
TEST tPLH/tPHL S1 Open VCC < 2.7V 2.7-3.6V VI VCC 2.7V
VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL
SV00903
Figure 3. Load circuitry for switching times.
VM t PLH t PHL
NOTE: The shaded areas indicate when the inputis permitted to change for predictable output performance. SV00489
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays, clock pulse width, nD to nCP set-up times, the nCP to nD hold times, output transition times and maximum clock pulse frequency.
VI nCP INPUT GND VI nS D INPUT GND VI nR D INPUT GND VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL VM tPHL tPLH tPLH VM tPHL VM tW VM tW VM trem
SV00490
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD to nCP removal time.
1998 Jun 17
6
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74A
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1998 Jun 17
7
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74A
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
1998 Jun 17
8
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
1998 Jun 17
9
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 06-96 9397-750-04487
Philips Semiconductors
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